This invention relates to the field of electronic signal timing delay devices. More particularly this invention relates to a new and improved bonding layer utilized in conjunction with a rolled electronic component suitable for use on a printed wiring board and which is capable of adjusting the arrival time of signals in high speed logic systems (time delay line).
It is well known in the electronic circuitry art that for a digital network to function correctly, certain logic variables must change state at accurately controlled points in time relative to one another. As a consequence, the precise control of signals is an important concern in printed circuit board (PCB) or wiring board (PWB) design. This concern has become especially critical with the advent of high speed digital logic networks.
Time delay lines are used in the electronics industry to adjust the timing of electronic signals. U.S. patent application Ser. Nos. 760,818 (now U.S. Pat. No. 4,675,625) and 761,007, (now U.S. Pat. No. 4,675,627, assigned to the assignee hereof, all of the contents of which are incorporated herein by reference, relate to such electronic signal time delay devices. The signal path delay devices of U.S. Pat. Nos. 4,675,627 and 4,675,627 made by forming a laminate of highly conductive are made by forming a laminate of highly conductive metal bonded to a thin, flexible dielectric film. The metal is deposited or etched so as to produce a pattern consisting of a signal line in a ground shield. The signal line is preferably serpentine (i.e., zig-zags) and makes one or more passes back and forth on the dielectric film. A ground plane is also provided via the conductive metal and surrounds the signal line, separated thereby by a small gap on both sides of the line. Two Pads or other means are provided at the ends of the signal line to interconnect the same with the circuit in which it is used. This coplanar flexible circuit is then rolled up tightly into a cylindrical shape. Significantly, the serpentine pattern of the signal line must be designed so that when the flexible circuit is rolled up, the signal line will overlap the ground plane of the next layer (not the signal line of the next layer). While there will be some overlap of the signal lines, such overlap should be at right angles and with a minimal break in the ground shield. The rolled circuit has typically used adhesive to hold it together and to stabilize the effect of the dielectric. Thereafter it may be packaged and marked by a number of well known methods.
In U.S. Pat. No. 4,675,627, the delay of the delay line is substantially increased (without increasing the line length of the circuit) by utilizing a dielectric and/or adhesive having high permeability. The use of a high permeability dielectric and/or adhesive will minimize the size, cost and resistive losses of the time delay device.
The signal time delay device of the prior patent applications have many advantages and features over both currently used delay lines as well as over prior art micro strip flexible circuit delay lines. Accordingly, the signal delay devices of U.S. Pat. Nos. 4,675,625 and 4,675,627 will provide a standard electronic component to be used on high speed logic boards, which will provide an accurate fixed time delay for high speed electronic signals; this time delay being provided with minimum distortion and degradation of the delayed signal. Additionally, the delay device of the prior applications is of compact size and is extremely economical to manufacture in high volume production.
While well suited for its intended purposes, there is a perceived problem with respect to several electrical and mechanical characteristics of a delay line which has been rolled using an adhesive system such as those used conventionally in flexible circuit constructions. Electrically, such conventional adhesive systems (i.e., acrylic, epoxy or phenolic-butyral) are relatively high in dielectric constant (DK) (3.0-4.5). A lower DK is advantageous in the delay device as it allows thinner constructions and provides improved signal integrity. Also, conventional adhesives are relatively low softening temperature materials which can lead to delamination and unrolling of the delay line at solder temperature. The conventional adhesives also would degrade at significant rates with time at temperatures below the solder temperatures (e.g., 150.degree.-260.degree. C.) which could also lead to delamination and changed electrical performance. Any amount of delamination can change the electrical performance and can also permit solder flux and other contaminants to enter the rolled circuit leading to corrosion.